There is a class of nonvolatile memory devices known as "flash EEPROMs" (electrical erasable programmable read only memory devices). The operation and structure of such devices is discussed in U.S. Pat. No. 4,698,787 issued Oct. 6, 1987, to Mukherjee et al., the disclosure of said patent being incorporated herein by reference. Another discussion respecting the operation and structure of flash EEPROM devices may be found in IEEE Journal of Solid State Circuits, Vol. SC-22, No. 5, October, 1987, pages 676-683 in an article entitled, "A 128K flash EEPROM Using Double-Polysilicon Technology" by Gheorghe Samachisa et al., the disclosure of said article being incorporated herein also by reference. A key feature of "flash" EEPROM's which distinguishes them from standard EEPROM's is that a select transistor is not included on a one-for-one basis with each floating gate transistor to select one memory cell for erasing. Instead, the memory cells of a flash EEPROM chip are erased in bulk, i.e., either the entire chip or by paged groups, commonly known as sectors. Each sector has a large number of floating gate transistors. For example, a 4 million bits (4 Mbit) flash EEPROM chip may have 8 equal size sectors of 64 thousand (64K) bytes each (each byte is equal to 8 bits and each bit is represented by one floating gate transistor). Typically, any combination of sectors, including all the sectors (i.e., the entire chip), can be concurrently erased. Elimination of the select transistor allows for smaller cell size and this gives the flash EEPROM an advantage in terms of manufacturing yield over a comparably sized (in terms of memory capacity) standard EEPROM.
A plurality of flash EEPROM cells may be formed on a semiconductor substrate (i.e., a silicon die) to each comprise a N-type source region integrally formed within a P portion of the substrate, a N-type drain region integrally formed within the P substrate portion and spaced apart from the source region, a P-type channel region interposed between the source and drain regions, a floating gate electrode insulatively spaced by a short distance (for example, 100 angstroms) above at least one of the source and drain regions, and a control gate electrode insulatively disposed above the floating gate electrode.
According to conventional operation, a flash EEPROM memory cell is "programmed" by inducing hot electron injection from a portion of the substrate (for example, a channel section near the drain region) to the floating gate. Electron injection carries negative charge into the floating gate. This injection mechanism is normally induced by grounding the source region and a bulk portion of the substrate, applying a relatively high positive voltage to the control electrode, for example, +12 Volts (V), to create an electron attracting field and applying a positive voltage of moderate magnitude (i.e., approximately +6 V to +9 V) to the drain region in order to generate "hot" (high energy) electrons. After sufficient negative charge accumulates on the floating gate, the negative potential of the floating gate raises the threshold voltage of its field effect transistor (FET) and inhibits current flow through the channel during a subsequent "read" mode. The magnitude of the read current is used to determine whether an EEPROM cell is programmed or not. Typically, in the read mode, a relatively low positive voltage, for example, +1.5 V, is applied to the drain, +5 V is applied to the control electrode and 0 V is applied to the source region of the memory cell.
The act of discharging the floating gate is called the erase function for a flash EEPROM cell. This erasure function is typically carried out by a Fowler-Nordheim tunneling mechanism between the floating gate and the source region of the transistor (source erase or negative gate erase) or between the floating gate and the substrate (channel erase).
A source erase operation is induced by applying a high positive voltage to the source region and a 0 V to the control gate and the substrate, while floating the drain of the respective memory cell. This positive voltage may be approximately +12 V.
While the source erase operation have the advantages of providing a tight after erase Vt distribution due to the use +12 V at the source for the erasure (a discussion of the control of after erase Vt distribution using high voltage source erase may be found in IEDM, 1992, pages 595-598 in an article entitled "Comparison of Current flash EEPROM Erasing Method: Stability and How to Control" by K. Yoshikawa et al., the disclosure of said article being incorporated herein by reference) and being insensitive to defects in the channel because all tunneling are through the small area of source to gate overlap, a number of drawbacks exist. First, an external power source of approximately +12 V is needed. Since different voltages, i.e., +4 V to +9 V, +5 V and +12 V, need to be applied to the drain and source regions of the device during programming, reading and erasure, it is often necessary to provide two off-chip power supplies for operating integrated circuit chips having such flash EEPROM's cells. There is a long-felt desire within the industry to develop a flash EEPROM integrated circuit chip which may be operated from only one power supply, i.e., +5 V or less. Unfortunately, the magnitude of source to substrate current tends to be relatively high during erasure, on the order of approximately 1 microamp per cell, and as a result, the power requirement of a memory chip having one million or more memory cells (a 1 megabit chip) can be as high as one ampere. Self-limiting techniques are often used for reducing this source to substrate current to levels of approximately 20 to 30 milliamps, but even at these levels, it is difficult to provide enough current from an on-chip charge pump circuit. An external power source of approximately +12 V or higher is needed.
A second drawback of the source erase technique is the difficulty in providing high density flash EEPROM cell arrays due to the requirement of a double-diffused source structure. When source erase technique is used, a relatively high reverse voltage is generated between the source and substrate during erasure. (The P-type substrate is at 0 V and the N+ type source region is at +12 V). A double-diffused source structure is normally employed (such as disclosed in Mukherjee, U.S. Pat. No. 4,698,787) to protect against undesirable reverse voltage breakdown of the source to substrate PN junction. The fabrication of a double-diffused structure requires an additional implantation step and a critical masking step which demands very precise alignment of the mask relative to the floating gate and the control gate of each cell within the flash EEPROM cell arrays. These additional steps, specifically the critical masking step, increase the cost and complexity of the fabrication process and reduce production yields. In addition, the double-diffused source structure occupies more substrate area than would otherwise be occupied by a single-diffused source structure and accordingly it is difficult to provide high density flash EEPROM cell arrays on relatively small dies in a cost-effective manner.
A third drawback associated with the source erasure of flash EEPROMs wherein a relatively high positive voltage (i.e., +12 V) is developed at the source region, is that there is a substantial probability that high energy holes ("hot" holes generated by a so called "avalanche effect") might be formed at a surface portion of the source to substrate junction and that these holes will become trapped in the thin dielectric underlying the floating gate. To a similar extent, there is a further danger that additional high energy holes will be generated by a so called band to band tunneling conduction mechanism and these will also be trapped in the gate dielectric. The distinction between avalanche generated holes and band to band generated is discussed in an IEEE paper entitled, "Drain-Avalanche and Hole-Trapping Induced Gate Leakage in Thin-Oxide MOS Devices" by Chi Chang, et al., IEEE Electron Device Letters, Vol. 9, No. 11, November, 1988, pages 588-590. This article is incorporated herein by reference.
The production of avalanche generated holes at the surface of the dielectric below the floating gate is undesirable because it can interfere with reliable programming, reading and erasure of randomly located memory cells (i.e., the gate disturb phenomenon), because it tends to decrease the charge retention time of the floating gate (holes trapped in the gate dielectric can migrate upwardly into the floating gate to neutralize the negative program charges in the floating gate). Specifically, during erasure, some memory cells may produce more hot holes than others and consequently their floating gates will be discharged at a faster rate. This creates a non-uniform erasure throughout the memory chip. Those holes which do not migrate to the floating gate during erasure can remain in the dielectric for random periods of time and then migrate to the floating gate, where they neutralize charge that is to be retained. Furthermore, during programming, trapped holes in the dielectric can cause undesirable programming of nonselected cells. These undesirable phenomena are further described in an article entitled, "Degradations Due to Hole Trapping in Flash Memory Cells" by Sameer Haddad et al., IEEE Electron Device Letters, Vol. 10, No. 3, March, 1989, pages 117-119; said article being incorporated herein by reference. A further disadvantage of operation in the avalanche breakdown region is that it increases the magnitude of source current during erasure.
A fourth drawback of the source erase technique is due to electron and hole injection into the source region, causing mobility degradation on the source region. This degradation may impair the performance of the flash EEPROM cell.
A negative gate erase operation is induced by applying +5 V to the source region, a negative voltage to the control gate and 0 V to the substrate, while floating the drain of the respective memory cell. This negative voltage may be as much as -10 V. One of the advantages of the negative gate erase technique is the reduction in the source voltage to +5 V during erasure which substantially reduce the probability of high energy holes resulting in improved reliability. The other advantages of the negative gate erase technique is that it only requires a single +5 V power supply (instead of a +12 V power supply as in the case of the source erase technique) and it is insensitive to defects in the channel because all tunneling are through the small area of source to gate overlap. However, a number of drawbacks may be associated with the negative gate erase operation.
First, a negative charge pump is needed to provide the -10 V required at the control gate for erasure. Also, in case of a +3 V supply voltage operation, a positive charge pump may also be needed to provide the +5 V required for the source region during erasure. A second drawback is that the negative gate erase technique fails to provide high density EEPROM cell arrays because a double-diffused source structure is found to be necessary in many instances. Third, the after erase threshold voltage (Vt) distribution of the flash EEPROM cells is wider, which is undesirable. A tight after erase V.sub.t distribution is desirable because designed safety margins accounting for the distribution of the threshold voltages, especially sense amplifiers, can be reduced.
A channel erase operation is induced by applying a high positive voltage to the substrate and a 0 V to the control gate, while floating both the source and the drain regions of the respective memory cell. This positive voltage may be as high as +12 V. One of the advantages of the channel erase technique is that a single-diffused source structure can be used, which allows a reduction in the size of the memory cells, resulting in a flash EEPROM array with higher density. The other advantage is that a separate +12 V power supply is not needed since the substrate high voltage can be pumped from a +3 V power supply. Furthermore, since the source is floating, there is generally no high energy holes related reliability problem.
Again, a number of drawbacks may be associated with the channel erase operation. First, since the erase involved tunneling through the whole channel, the channel erase operation is very sensitive to defects found in the channel. This could lead to potential yield problems. Second, the after erase Vt distribution of the flash EEPROM cells is widest among the three conventional erase techniques, which is very undesirable.
Hence, there is a need to have a method and a flash EEPROM memory cell structure that allows erasure operation with the advantages of the conventional erasure techniques in combination, while minimizing the drawbacks associated with such conventional techniques. The present invention addresses such a need.